TAPO - Intellectual Property


This guide is designed to provide Trusted Access Program Office (TAPO) customers with information about obtaining and using Intellectual Property (IP) from the TAPO portfolio. The guide describes:

The guide also includes a basic listing of available IP, the forms used to apply for access and a list of resources where help can be obtained in searching for IP.

TAPO IP Acquisition Flow

The TAPO IP acquisition flow is predicated on the need to provide robust customer support with minimal paperwork. From the beginning to the end of the customer's IP search, they will be paired with a TAPO Customer Application Engineer (CAE), the TAPO IP Coordinator (IPC) and a GLOBALFOUNDRIES U. S. 2 LLC (GFUS2) Field Application Engineer (FAE). With the help of these individuals, the customer will receive instruction in both business and technical areas related to gaining access to existing IP or developing a new IP block.

For every customer design needing IP, the TAPO office will sponsor a kickoff meeting with GFUS2, the appropriate TAPO personnel and the customer to vet the design requirements and to ensure all the parties involved have context for the IP requests. This process is summarized in the following steps:

The following picture illustrates the IP process.

A flowchart illustrating the IP process.

TAPO IP Portfolio

The TAPO portfolio includes almost two hundred entries in the following technology nodes:

Standard cell, GPIO and SRAM libraries exist in many of these technologies. Specialty I/O cells such as LVDS, HSTL and SSTL, PLLs and oscillators also exist for all the 180nm through 32nm processes. Microprocessors such as ARM926E-J, ARM966E-S, ARM7TDMI, PowerPC 440 and PowerPC 405 may be found in 130nm and 90nm nodes as well. Additionally, varying sized efuse macros may also be found in the 180nm through 32nm nodes. TAPO has also been able to acquire access to standard cell libraries, GPIO and memories for some of the SiGe technologies. Datasheets, product briefs and more detailed information may be obtained by request through your TAPO IP Coordinator.

ARM libraries are available for the CMRF8SF, CMOS9SF, CMS9FLP, SOI12S0 and 32SOI technologies. The libraries typically consist of standard cells, SRAMs, register files, ROMs and wirebond I/O cells. Many of these library elements are offered in a variety of FET types. Additionally, the user can expect to find support for a wide range of process-voltage-temperature (pvt) timing. In collaboration with GFUS2, TAPO is involved in helping to ensure that these libraries have support for multiple EDA views, pvt points and metal stacks.

IP through the TAPO contract typically comes in several different forms:

In each of these cases, TAPO is available to help the customer work through options to arrive at a solution that best fits their design requirements.

TAPO is now making the following IP blocks available in the 130nm through 32nm digital processes:

IP that does not fall into these categories will require customer funding.

TAPO IP Licensing Rules

Using IP from the Trusted Foundry portfolio is subject to certain licensing rules. A top-level review of these rules follows. This review is not a full legal statement of the user's rights, but is meant to be an overview of the rules. A complete understanding of the limitations may be obtained through GFUS2.

For more information about IP license use, please see the GFUS2 IP license agreement or contact GFUS2.

TAPO IP Maintenance

TAPO offers an IP support package termed "maintenance." The goal of a maintenance plan is to ensure that the IP in the TAPO portfolio remains up-to-date with GFUS2's latest technology Process Design Kit (PDK). As technologies mature, new devices/solutions may be added or design rules modified. When this happens, GFUS2 will publish a new design kit and new DRC rules. These technology updates can cause the need for updates to existing IP. To proactively address this requirement, TAPO has worked with GFUS2 to develop a maintenance plan that the customer can purchase for their IP. An IP maintenance package includes:

Any IP that TAPO considers part of its general offering (see the list of prepaid IP in Portfolio) will be covered by TAPO with a maintenance package. The customer can expect two to four weeks for GFUS2 to generate an IP maintenance quote for IP that does not fall under the TAPO umbrella.

TAPO IP Resources

It is common for a customer to have questions when going through the various stages of the design cycle. With this in mind, the following resources may be helpful:

Trusted IP

TAPO customers might have security concerns regarding IP in the TAPO portfolio. Many projects using the Trusted Access Program Office are seeking trusted IP. At present, there is no certification process for vetting IP purchased by TAPO. While recognizing the concerns that exist in the defense community, there is neither a mandate nor identified resource to drive this kind of effort. Instead, TAPO and GFUS2 have insisted on full views of the IP so that the concerned customer can perform their own security vetting to ensure a successful project.

TAPO IP Business Essentials

While most IP in the TAPO library can be accessed and used at no cost to the customer, there are some that can only be accessed with a customer funded user fee. Another occasion requiring customer funding occurs when GFUS2 engineering services are required. This happens when an existing IP block needs some modification, additional EDA views are added or when the customer seeks to have a new block developed from scratch. A third instance occurs when the customer is seeking an IP maintenance plan.

In support of the funding effort, TAPO and GFUS2 have put together two tools for making purchases. These tools are:

Quotes and RFIs are delivered to the TAPO office for reprocessing and then forwarded to the customer.

There are two paths from which a customer can receive an actionable quote, depending on the funding mechanism. The “government sponsor to TAPO” funding path is known as the Military Interdepartmental Purchase Request (MIPR) path and the “contractor to TAPO” funding path is known as the Independent Research and Development (IR&D) path. Customers should contact their CAE for further assistance if they require a transfer of contractor funds through the IR&D process. TAPO will supply MIPR quotes directly to the government sponsor and IR&D quotes will be supplied through an IR&D contract vehicle. Once the quote is actionable and TAPO receives the funding through the appropriate path, the TAPO office will submit a purchase order to GFUS2 and the requested work will begin.

Suggestions for Avoiding Common IP Pitfalls

Ensuring that one's IP is correct for a particular chip can be a difficult part of the design preparation process. Here are some suggestions for avoiding common pitfalls involved with acquiring IP.