TAPO IP
TAPO IP

This guide is designed to provide Trusted Access Program Office (TAPO) customers with information about obtaining and using Intellectual Property (IP) from the TAPO portfolio. The guide describes:

  • The process for acquiring IP
  • How to pay for it
  • How to get technical information
  • Licensing information
  • Available IP maintenance plans
  • A list of some common IP pitfalls

The guide also includes a basic listing of available IP, the forms used to apply for access and a list of resources where help can be obtained in searching for IP.

TAPO IP Acquisition Flow

The TAPO IP acquisition flow is predicated on the need to provide robust customer support with minimal paperwork. From the beginning to the end of the customer's IP search, they will be paired with a TAPO Customer Application Engineer (CAE), the TAPO IP Coordinator (IPC) and a GLOBALFOUNDRIES U. S. 2 LLC (GFUS2) Field Application Engineer (FAE). With the help of these individuals, the customer will receive instruction in both business and technical areas related to gaining access to existing IP or developing a new IP block.

For every customer design needing IP, the TAPO office will sponsor a kickoff meeting with GFUS2, the appropriate TAPO personnel and the customer to vet the design requirements and to ensure all the parties involved have context for the IP requests. This process is summarized in the following steps:

  • Kickoff Meeting - a conference call is held between GFUS2, TAPO and the customer to discuss the IP being sought.
  • IP Request Review - if the IP being requested does not currently exist, another conference call is held between TAPO, GFUS2 and the customer to review the statement of work (SOW) for the new piece of IP.
  • IP Update - the TAPO IP Coordinator provides status to the customer as their request is being processed.

The following picture illustrates the IP process.

General IP Flow Image

TAPO IP Portfolio

The TAPO portfolio includes almost two hundred entries in the following technology nodes:

  • CMRF6SF
  • CMRF7SF
  • SIGE7WL
  • CMRF8SF
  • SIGE8HP
  • SIGE8WL
  • CMOS9SF
  • CMS9FLP/9RF
  • SIGE9HP
  • CMS10SF
  • CM10LPL/10RFe
  • SOI12S0
  • 32SOI

Standard cell, GPIO and SRAM libraries exist in many of these technologies. Specialty I/O cells such as LVDS, HSTL and SSTL, PLLs and oscillators also exist for all the 180nm through 32nm processes. Microprocessors such as ARM926E-J, ARM966E-S, ARM7TDMI, PowerPC 440 and PowerPC 405 may be found in 130nm and 90nm nodes as well. Additionally, varying sized efuse macros may also be found in the 180nm through 32nm nodes. TAPO has also been able to acquire access to standard cell libraries, GPIO and memories for some of the SiGe technologies. Datasheets, product briefs and more detailed information may be obtained by request through your TAPO IP Coordinator.

ARM libraries are available for the CMRF8SF, CMOS9SF, CMS9FLP, SOI12S0 and 32SOI technologies. The libraries typically consist of standard cells, SRAMs, register files, ROMs and wirebond I/O cells. Many of these library elements are offered in a variety of FET types. Additionally, the user can expect to find support for a wide range of process-voltage-temperature (pvt) timing. In collaboration with GFUS2, TAPO is involved in helping to ensure that these libraries have support for multiple EDA views, pvt points and metal stacks.

IP through the TAPO contract typically comes in several different forms:

  • Existing IP - available for download pending access request
  • Existing IP with limited flexibility - this IP is available for download, but may need additional EDA views that could require customer funding
  • ASIC IP - this is IP that exists in GFUS2's ASIC flow and can be sized for porting to GFUS2's Foundry Flow with customer funding
  • New IP - new IP that the customer wants to have GFUS2 develop

In each of these cases, TAPO is available to help the customer work through options to arrive at a solution that best fits their design requirements.

TAPO is now making the following IP blocks available in the 130nm through 32nm digital processes:

  • Standard Cells
  • Wirebond and Area Array GPIO
  • SRAMs
  • EDRAM (in some technologies)
  • Register Files
  • ROMs
  • Wirebond and Area Array LVDS, HSTL and SSTL
  • 128-bit eFuse Macros
  • Standard PLLs
  • Standard Oscillators
  • TVSense

IP that does not fall into these categories will require customer funding.

TAPO IP Licensing Rules

Using IP from the Trusted Foundry portfolio is subject to certain licensing rules. A top-level review of these rules follows. This review is not a full legal statement of the user's rights, but is meant to be an overview of the rules. A complete understanding of the limitations may be obtained through GFUS2.

  • All IP in the TAPO IP portfolio is only for use in U.S. Government sponsored programs that access GFUS2 through TAPO. Commercial or other non-U.S. Government applications require the user to resolve license, use and payment agreements with GFUS2, and/or the IP vendor, as applicable.
  • While most of the IP in the TAPO portfolio carry unlimited use licenses, some will require the customer to purchase a use fee. Contact a TAPO Customer Application Engineer for a listing of which IP blocks may require this.
  • Not all TAPO IP has unlimited use licenses. For those customers who acquire a single use license, a single use is defined as follows:
    • Each use of IP in silicon is a chargeable use. Each use covers the tapeout of a prototype and production run so long as the production/re-spin run is being made to: fix an error, change timing or type of memory, update GFUS2 IP, or change less than 15% of the logic gates.
    • If a customer produces a prototype, but does not move to production, that counts as one use. The license fee is not refunded, nor can it be transferred to another project.
    • For non-silicon validated IP, the customer may produce a test chip to validate the IP without charge as long as the sole purpose of the tapeout is IP verification. The test chip may not be used to build samples.
  • All TAPO IP will require the customer to sign or agree to GFUS2’s non-disclosure agreement, letter of liability and a software license agreement. These agreements cover only the company signing them. If the customer is subcontracting their design services, the subcontractor may be required to sign similar agreements. This can take some time to bring to closure when third party IP providers are involved. The rule of thumb is that all parties who will have access to GFUS2 data must sign the agreements.

For more information about IP license use, please see the GFUS2 IP license agreement or contact GFUS2.

TAPO IP Maintenance

TAPO offers an IP support package termed "maintenance." The goal of a maintenance plan is to ensure that the IP in the TAPO portfolio remains up-to-date with GFUS2's latest technology Process Design Kit (PDK). As technologies mature, new devices/solutions may be added or design rules modified. When this happens, GFUS2 will publish a new design kit and new DRC rules. These technology updates can cause the need for updates to existing IP. To proactively address this requirement, TAPO has worked with GFUS2 to develop a maintenance plan that the customer can purchase for their IP. An IP maintenance package includes:

  • A declared period of time (design cycle) in which the IP update is current with the latest technology PDK.
  • A refresh to the subject IP within ten weeks of a technology PDK update.
  • A waiver process to evaluate and authorize a customer tape-out with a design kit to a down-level technology PDK while awaiting the IP refresh.

Any IP that TAPO considers part of its general offering (see the list of prepaid IP in Portfolio) will be covered by TAPO with a maintenance package. The customer can expect two to four weeks for GFUS2 to generate an IP maintenance quote for IP that does not fall under the TAPO umbrella.

TAPO IP Resources

It is common for a customer to have questions when going through the various stages of the design cycle. With this in mind, the following resources may be helpful:

  • GFUS2 Field Application Engineer (FAE) - GFUS2 assigns an FAE to support TAPO customers with respect to IP. The assigned FAE will be introduced during the initial IP Kickoff meeting.
  • TAPO Customer Application Engineer (CAE) - this is the customer's main point of contact throughout the entire engagement with TAPO.
  • TAPO IP Coordinator - this is TAPO's chief contact for TAPO IP.
  • TAPO Website - this website offers information on services customers could obtain through TAPO.
  • Foundry Tech - all customers who are licensed to receive GFUS2 IP can receive technical support. Interested customers should contact their CAE for further details or assistance.
  • GFUS2 Customer Connect - GFUS2 posts a large volume of technical data on the website where they house their IP. A Customer Connect account may be obtained by request to the GFUS2 FAE.

Trusted IP

TAPO customers might have security concerns regarding IP in the TAPO portfolio. Many projects using the Trusted Access Program Office are seeking trusted IP. At present, there is no certification process for vetting IP purchased by TAPO. While recognizing the concerns that exist in the defense community, there is neither a mandate nor identified resource to drive this kind of effort. Instead, TAPO and GFUS2 have insisted on full views of the IP so that the concerned customer can perform their own security vetting to ensure a successful project.

TAPO IP Business Essentials

While most IP in the TAPO library can be accessed and used at no cost to the customer, there are some that can only be accessed with a customer funded user fee. Another occasion requiring customer funding occurs when GFUS2 engineering services are required. This happens when an existing IP block needs some modification, additional EDA views are added or when the customer seeks to have a new block developed from scratch. A third instance occurs when the customer is seeking an IP maintenance plan.

In support of the funding effort, TAPO and GFUS2 have put together two tools for making purchases. These tools are:

  • Request for Quote (RFQ) - Through the TAPO IP Coordinator, the customer can submit a CRF request to have an actionable quote created that includes a description of the work to be done, the schedule and cost. These typically take about a month to generate. If the quote involves third party vendors, the schedule can be longer. Quotes typically have a 30 day expiration time.
  • Request for Information (RFI) - Through the IP Coordinator, the customer can submit a CRF request for information. This is a non-actionable quote used to provide estimated costs for performing the requested work. An RFI is not a commitment to perform the work. An RFI typically takes two weeks to generate.
  • The customer will receive the RFQ or RFI from the TAPO office.

Quotes and RFIs are delivered to the TAPO office for reprocessing and then forwarded to the customer.

There are two paths from which a customer can receive an actionable quote, depending on the funding mechanism. The “government sponsor to TAPO” funding path is known as the Military Interdepartmental Purchase Request (MIPR) path and the “contractor to TAPO” funding path is known as the Independent Research and Development (IR&D) path. Customers should contact their CAE for further assistance if they require a transfer of contractor funds through the IR&D process. TAPO will supply MIPR quotes directly to the government sponsor and IR&D quotes will be supplied through an IR&D contract vehicle. Once the quote is actionable and TAPO receives the funding through the appropriate path, the TAPO office will submit a purchase order to GFUS2 and the requested work will begin.

Suggestions for Avoiding Common IP Pitfalls

Ensuring that one's IP is correct for a particular chip can be a difficult part of the design preparation process. Here are some suggestions for avoiding common pitfalls involved with acquiring IP.

  • The customer should consider IP acquisition the critical path in their design cycle. When acquiring IP, there are many variables. Getting access to an IP block may involve one or more of the following efforts: a business cycle, legal cycle (Confidential Disclosure Agreement, Design Kit License Agreement), requirements collection cycle and development time. Each of these cycles has its own challenges. Time should be allotted for the unexpected.
  • The customer should ask about metal stack support. Some IP blocks are metal stack dependent and may not have support for the metal stack that a customer's design is targeting.
  • The customer should ask about pvt support. The TAPO IP portfolio consists of IP developed by many customers and vendors. While TAPO does its best to make its IP look like elements of a common library, there are still IP blocks with timing support for limited corners.
  • The customer should ask about available licenses. Not all pieces of IP in the TAPO library have unlimited uses. The customer may be asked to fund a usage fee.
  • The customer should ask about how current the IP block is to the latest GFUS2 design rules. Some blocks available to TAPO are older and may not be current with the latest GFUS2 Process Design Kit (PDK).
  • The customer should ask about risk factors. Some IP blocks are very complex. It is good to know if the IP is silicon verified.
  • The customer should ask about how using design subcontractors or university design services may impact their ability to obtain IP.
  • The customer should ask about where they will be getting technical support should they need it.
  • The customer should ask if the IP block they are seeking requires the use of other IP blocks.
  • The customer should make no assumptions